1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device, and more particularly to such a semiconductor integrated circuit device as a semiconductor memory device in which metal wires are arranged as assist wires in parallel to word lines in order to operate the word lines at a high speed.
2. Description of the Related Art
A method in which word lines and metal wires (the description is made on the assumption that the metal wires are formed of aluminum) are arranged in parallel to each other and connected at certain intervals (hereinafter referred to as "an aluminum assist method for word lines") has been known as a technique for operating word lines of a static random access memory (hereinafter referred to as "SRAM").
The construction of SRAM using the conventional aluminum assist method for word lines will be described with reference to FIG. 1. FIG. 1 is a diagram showing the construction of SRAM using the conventional aluminum assist method for word lines.
In FIG. 1, reference numeral 1 represents word lines formed of polysilicon, reference numeral 2 represents assist wires disposed in parallel to the word lines so as to form the second aluminum wiring layer, and reference numeral 3 represents contacts for connecting the word lines and the aluminum assist wires. In FIG. 1, the word lines 1, the contacts 3 and the assist wires 2 are illustrated as being arranged on the same plane, however, they are actually arranged longitudinally as shown in FIG. 2 which is a vertical cross-sectional view of the end portion of the word lines. Reference numeral 4 represents digit lines which is disposed so as to form the first aluminum wiring layer, and reference numeral 5 represents an X decoder for selecting a word line.
Reference numeral 6 represents a peripheral circuit A formed at one end portion of the digit line 4, and reference numeral 7 represents a peripheral circuit B formed at the other end portion of the digit line 4. The peripheral circuit A includes a system extending from an address buffer circuit to a decoder circuit for selecting a word line, a system extending from an address buffer circuit to a decoder circuit for selecting a division number (hereinafter referred to as "section") of the word lines, a clock system circuit for controlling the inside on the basis of a clock which is generated due to switching of addresses, a control system circuit of CE2, a control system circuit of WE, and pads for each address, control system, GND, etc. Further, the peripheral circuit B includes a system extending from an address buffer to a decoder circuit for selecting a digit line, a clock system circuit for controlling the inside on the basis of a clock generated due to the switching of the addresses, a control system circuit for CE1 and OE, a sense amplifier circuit, an input/output transistor, and pads for each address, CE1, input/output, VCC, etc.
Reference numerals 8 and 9 represent array portions which are designed in a cell-pitch structure and disposed around the digit lines. Reference numerals 10 and 11 represent signal/power source lines through which signals are transmitted between the peripheral circuits A and B. The signal lines include a signal line for a control system of CE1, CE2 system for controlling the switching between a stand-by state and an active state, a signal line for a control system of WE for controlling the switching between WRITE and READ, a signal line for the clock system, a signal line for selecting a section, etc.
In FIG. 1, reference numeral 14 represents a semiconductor chip on which the integrated circuit is formed. Memory cells which are not shown in FIG. 1 are arrayed in an area where the word lines and the digit lines are extended. Each memory cell is connected to both a word line and a digit line. In FIG. 2, reference numeral 13 represents a memory cell array area, and reference numeral 15 represents an insulation layer within which the word lines 1, the assist wires 2, the contacts 3, the digit lines 4 and the signal/power source lines 10, 11 are formed.
The above is a general layout construction of SRAM.
Next, the high-speed operation of the word lines by the aluminum assist method for the word lines will be described with reference to FIGS. 3 and 4.
FIG. 3 is a partial construction diagram showing the connection relationship between the X decoder 5, the word lines 1 and the assist wires 2 of SRAM using the aluminum assist method of the word lines, and FIG. 4 is a partial construction diagram showing the connection relationship between the X decoder 5 and the word lines 1 of SRAM using no aluminum assist method for word lines. In FIG. 1, the contacts are formed at fixed intervals between the word lines and the aluminum assist wires. However, in FIG. 3, contacts 3 are formed at two positions of a near end portion and a far end portion relative to the X decoder 5.
In FIG. 3, reference numeral 1 represents a word line formed of polysilicon, reference numeral 2 represent an aluminum assist wire which is arranged in parallel to the word line, reference numeral 3 represents contacts for connecting the word line and the assist wire, and reference numeral 5 represents an X decoder for selecting a word line. In FIG. 4, reference numeral 1 represents a word line formed of polysilicon, and reference numeral 5 represents an X decoder for selecting a word line. The symbol L in FIGS. 3 and 4 represents the wire length of the word line.
In the SRAM using no aluminum assist method for word lines shown in FIG. 4, the time T which is required for the operation of selection or non-selection of word lines is expressed by the following equation for simplicity's sake: EQU T=crL.sup.2 ( 1)
Here, c represents capacitance of the word line per unit length, and r represents resistance of the word line per unit length. The portion of the word line which requires the longest operation time is located at the far end portion which is farthest from the X decoder 5.
In the SRAM using the aluminum assist method for word lines shown in FIG. 3, with respect to the time T required for the operation of selection or non-selection of word lines, the resistance of the aluminum assist wire is negligibly small as compared with that of the word line made of polysilicon, and thus the operation time of selection or non-selection of the aluminum assist wire can be neglected. Therefore, the longest time is required for the center position between the contacts. Further, the overall resistance is equal to 1/4 of that of the case of FIG. 4 and the capacitance which is driven by the X decoder is not varied. Therefore, the time T is expressed as follows: EQU T=(1/4)crL.sup.2 ( 2)
It is therefore apparent that the operation time is reduced to 1/4 as compared with the equation (1).
As is apparent from the foregoing description, the operation time for selection or non-selection of word lines can be reduced by applying the aluminum assist method for word lines to SRAM.
However, in the SRAM using the aluminum assist method for word lines, the assist wires are disposed in parallel to the word lines in the memory cell array area so as to form the second aluminum wiring layer, and thus it is impossible to arrange the signal lines and power source lines in parallel to the digit lines perpendicular to the word lines so as to form the second aluminum wiring layer in the memory cell array area. Further, the first aluminum wiring layer is used only for the digit lines, because the chip size is reduced and thus the digit line width and the digit line interval are normally set to design standard values of a diffusion process or near values and therefore, it is also impossible to arrange signal line or power source line other than the digit lines in the first aluminum wiring layer so as to be parallel to the digit lines. Therefore, as shown in FIGS. 1 and 2, the signal/power source lines 10, 11 must be disposed so as to separate from the memory cell array area. In FIG. 2 which is a cross-sectional view showing the word line end portion of the SRAM using the conventional aluminum assist method for word lines, it is shown that the signal/power source lines 10 are arranged outside of the memory cell array area 13 where the word lines 1, the assist wires 2, the contacts 3 and the digit lines 4 are disposed.
The signal lines are directed from the peripheral circuit A to the peripheral circuit B or from the peripheral circuit B to the peripheral circuit A, and have a length which is equal to or longer than the digit line length. Therefore, from the viewpoint of the operation timing of SRAM, the signal lines must be formed in the wiring layer having low resistance, so that the second aluminum or first aluminum wiring layer is required to be used. Further, it is necessary to design the signal lines so that the wire width thereof is set to not small value and the wire interval is as large as possible in order to reduce the signal delay from the peripheral circuit A to the peripheral circuit B or from the peripheral circuit B to the peripheral circuit A. With respect to the power source lines, power source lines having a large wire width are used in order to reduce the wire resistance as greatly as possible.
Since the wiring areas as described above are kept for the signal lines and the power source lines, the increase of the length of the semiconductor chip in the word line direction cannot be neglected. Although the values are varied in accordance with a specification of an article, for 1M SRAM having a design standard of about 0.4 .mu.m, the width of the power source lines is set to about 20 .mu.m, and the signal line area is set to 15 .mu.m because the number of the signal lines is equal to 5 to 10 (in this case, the width and interval are considered on the assumption that the number of signal lines is equal to 7.5). Therefore, assuming that totally four power source lines of VCC, GND are provided at both the sides, the increase of the length in the word line direction becomes about 100 .mu.m.
For an article of 0.4 .mu.m standard, the chip size is set so that the short side thereof is equal to about 3.5 mm and the long side thereof is equal to about 6.5 mm, and thus the area of the chip is set to about 22.75 mm.sup.2. Therefore, the chip size is made increased for the wiring area of the signal lines and the power source lines of FIG. 1 by at least 100 .mu.m.times.long side, that is, by about 3%. This induces a critical problem from the viewpoint of the recent trend of further increasing the integration degree of the semiconductor integrated circuits.